行为
功能 #3021
已关闭开始日期:
2024-11-05
计划完成日期:
2024-11-06
% 完成:
100%
预期时间:
描述
“DRL_POS_Trigger_DutyCycle_cfg” need to be selected in the dataset
Values range between 10-41%, 200Hz(If DRL input frequency>210Hz||<190Hz,software should ignore this PWM.)
Note1:Set ‘DRL_POS_Trigger_DutyCycle_cfg’ significantly higher/lower than BCM DRL direct wire duty cycle value to avoid the sampling error.
行为